Pitfalls in analog front-end design for DSP

The analog front end sets the noise floor of a DSP system. The ADC is only as good as the supply, the reference and the ground it sees. A clean algorithm cannot save a noisy front end, and every bit lost in the front end cannot be recovered by the algorithm.

The following pitfalls cost the most signal-to-noise ratio (SNR) in practice. Each one costs effective bits (ENOB). All of them can be avoided at schematic and layout time, before the first measurement.

DC/DC converter: ripple and skip mode

A switching converter produces output ripple at its switching frequency and its harmonics. Amplitude typically a few mV to tens of mV, frequency usually 500 kHz to 2 MHz. This ripple couples through the supply pins into reference and signal path and shows up in the ADC spectrum as a narrow spur, often right next to the signal of interest or on one of its aliases.

At light output loads many converters switch to a pulse-skipping or PFM (pulse frequency modulation) mode. The loop no longer switches at a fixed frequency with variable duty; instead it emits individual pulses whenever the output falls below a threshold. The effective switching frequency drops and becomes load-dependent. Instead of a clear spectral line, a broad noise pattern with sub-harmonics of the nominal switching frequency appears, and its position moves with the operating point. This pattern can land in the band of interest and is hard to filter there.

The pitfall is over-dimensioning the converter. Whoever sizes the current generously because the load is still undefined ends up running it in the partial-load range. That is exactly where skip or PFM mode kicks in.

• Choose forced-PWM. A converter in forced continuous conduction mode holds the spectral line at a known frequency. It can be filtered specifically or placed out of the band. The price is a slightly worse efficiency at very light load.
• Keep the switching frequency out of the band of interest. Place the nominal switching frequency and at least the first harmonic above the highest signal frequency of interest. For audio-range bands (up to 20 kHz) typical 1 to 2 MHz switching frequencies are enough; for high-resolution low-frequency measurements (below 1 kHz) an active choice pays off.
• Post-regulate. Put an LDO after the converter, with the caveat from the next section (PSRR at the ripple frequency).
• Size the load correctly. Choose the dimensioning so the converter stays in the PWM region during nominal operation, not in the skip region. Datasheet: check the “PWM/PFM boundary vs. load current” plot.

LDO: PSRR at the frequency of interest

The LDO as post-regulator is the standard tool to suppress converter ripple. What matters is the power supply rejection ratio (PSRR), the ratio between disturbance at the input and disturbance at the output, in decibels. At DC and low frequencies good LDOs reach 60 to 80 dB. As frequency rises PSRR falls, often to 30 to 50 dB at 100 kHz and below that in the megahertz range.

The pitfall is expecting the LDO to clean the converter ripple at every frequency. With 1 MHz converter switching frequency and 40 dB PSRR, 100 µV remain of a 10 mV ripple, enough to visibly disturb a 16-bit ADC at its reference.

• Read the PSRR curve. Check the value exactly at the ripple frequency of the upstream converter, not at DC. For cascaded systems (converter + LDO + reference LDO) multiply the PSRR per stage.
• Check the signal frequency. The PSRR at the system’s own signal frequencies (band of interest and ADC sample clock) also has to be right, because modulation products can land exactly there.
• Add HF filtering. For the frequency range the LDO no longer covers, put a passive filter in front: LC low-pass with cutoff a decade below the converter frequency, or a ferrite bead plus capacitor for 10 MHz and above. The ferrite bead acts as a resistor above its series resonance and has to fit the current (DC saturation current in the datasheet).

Anti-aliasing filter

An ADC samples at rate fs. Anything above half the sampling rate (Nyquist frequency) folds back into the baseband when sampled and is afterwards indistinguishable from the real signal. The anti-aliasing filter ahead of the ADC has to attenuate that range down to below the noise floor of the desired resolution.

The pitfall is a filter that is too shallow. A simple RC pole rolls off at -20 dB/decade and therefore needs several decades between cutoff and Nyquist to reach useful attenuation. For an ADC at 100 kSPS with signals up to 20 kHz that barely works: at Nyquist (50 kHz) an RC with 20 kHz cutoff gives only about 8 dB of attenuation, far too little to cut broadband noise from op-amp and reference at the top.

• Couple filter order to resolution. Rule of thumb: attenuation at fs/2 has to sit below the quantisation noise of the target resolution. For 12 bits that is about 74 dB, for 16 bits 98 dB. A fourth-order Butterworth with cutoff around fs/5 clears that comfortably.
• Use oversampling. Whoever runs the ADC well above the signal’s Nyquist rate (oversampling ratio 4 to 16) pushes the aliasing boundary far up and can live with a gentler analog order; the remaining attenuation is done by the digital filter.
• Mind the noise bandwidth. The -3 dB bandwidth of a filter is not its noise bandwidth. For a single-pole RC the equivalent noise bandwidth is π/2 times larger than the -3 dB point. Work with the noise bandwidth in the noise budget, not the -3 dB point.
• Limit the op-amp bandwidth. An op-amp with 10 MHz GBW delivers noise far beyond the band of interest at its output, running straight into the ADC without a filter. Deliberately limit the bandwidth via the feedback network.

Grounding and ground loops

Analog and digital ground belong tied together at exactly one point, typically directly under the ADC’s ground pin or at the ADC’s split-ground terminal (AGND/DGND). Digital return currents must not flow through the analog ground plane. If they do, they develop a voltage over the finite plane impedance that appears as a common-mode disturbance at the ADC reference.

A ground loop appears when two or more ground connections between boards form a closed ring. Potential differences between the reference points or external magnetic coupling (mains field, motor cables) drive a circulating current through this loop, which again ends up as ground voltage in the signal path.

At low frequencies (up to a few kHz) the single-point connection is clean. At higher frequencies the connection inductance dominates; a plane split with many short bonds between analog and digital regions (plane partitioning with dedicated return paths) becomes more robust than classical star grounding.

• Single-point connection under the ADC. Tie analog and digital ground together at exactly one point directly under the converter so the ADC reference return current does not flow through foreign impedance.
• Terminate cable shields by frequency. For low-frequency, sensitive signals (thermocouple, strain gauge) terminate the shield at the receiver end only, to avoid ground loops. For HF signals (Ethernet, USB) terminate at both ends because there capacitive coupling dominates.
• Plan the return path in the layout. Every signal current has a return current on the nearest reference plane. When the plane is broken under a signal trace, the return takes the detour and couples magnetically into neighbouring traces.

TVS and filter at the bus

Bus lines like RS-485, CAN or Ethernet carry transients (ESD, burst, surge per IEC 61000-4) and common-mode disturbances into the device. A transient voltage suppressor (TVS) clamps over-voltage below the allowable part voltage. A common-mode choke suppresses common-mode content without distorting the differential signal.

The pitfall is the TVS clamping capacitance. On a fast bus (CAN-FD from 2 Mbit/s, Ethernet 100BASE-T) a high capacitance distorts the signal edges and closes the eye diagram. For CAN-FD, TVS parts should stay under 10 pF per pin; for 100BASE-T noticeably below. That severely restricts the choice, because low-capacitance TVS parts usually have lower clamping power.

The second mistake is computing with the clamping voltage without accounting for series impedance. The TVS only clamps if the disturbance current does not rise faster than the TVS diode can react. A small series inductance or resistor between connector and TVS limits the rise rate and gives the TVS time to build up its clamping.

The bus is also a path for disturbances into the front end. If bus ground is not cleanly separated from the analog region, or if the TVS return current is routed through the analog plane, the bus disturbance runs straight into the signal path.

Layout: separate analog from digital

The switching node (SW node) of the DC/DC converter is the most aggressive aggressor on the board. Between the high-side and low-side MOSFETs, the voltage swings with a slew rate of several V/ns. The Fourier decomposition of these edges reaches into the low gigahertz range and radiates both directly (E-field over the SW-node area) and via the ripple currents in input and output loops (H-field via the loop).

• Protect sensitive nodes. Surround high-impedance nodes (reference inputs, ADC sample capacitor, filter intermediate nodes) with a guard ring on signal ground. Route the reference and the sample clock as short as possible, directly, and without vias through signal planes.
• Physically separate zones. Place analog and digital sections in their own zones on the board, with their own supply and ground polygons. Deliberately cross the boundary at one point so return currents are guided there.
• Keep distance from the switching node. The switching node and the commutation loop of the converter must not lie underneath or right next to the analog area. Rule of thumb: at least 5 mm horizontal distance and no shared reference plane between the SW node and the analog area.
• Route digital clock lines deliberately. Clock lines (SPI, I²C, SDIO to the ADC) running parallel to sensitive traces couple in crosstalk. Cross at right angles when unavoidable, otherwise spacing and a reference-plane guard.

Takeaway

The front end is won in the detail: supply, reference, ground, filter, layout. None of these pitfalls is spectacular, and none of them show up in the first functional test where the ADC measures a clean sine test signal. They surface as spurs in the spectrum, as reduced ENOB compared to the datasheet value of the ADC, and as missing bits at the end of the processing chain.

Ruling them out at schematic and layout time saves the long hunt for the noise source in the finished device. A change at the schematic takes minutes, at the layout hours, at the fabricated prototype weeks. That is the real economics of front-end care.

Keywords: analog front end, DSP, ADC, SNR, ENOB, DC/DC ripple, PFM skip mode, LDO PSRR, anti-aliasing filter, oversampling, noise bandwidth, grounding, star ground, EMC layout, bus TVS, CAN-FD signal integrity, electronics engineering Switzerland, swissEmbedded PCB design Aargau